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Documentation

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"Transparent Mode" Optical DAQ guide

 

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HDL Framework installation guide

 

bulletECS registers and ram definitions you can find for each version under "VHDL Framework".

 

bulletTELL1 internal "Data transport format" defines the data format used to transmit data between PP-FPGA and SyncLink-FPGA

 

bulletCluster algorithm used for VELO and ST Clusterization for VELO and ST

 

bulletBank data format for Velo and ST

    VELO_ST_proc_full_bank

    VELO_zero_suppressed_bank

    ST_zero_suppressed_bank

    VELO_ST_non_zero_suppressed_bank

    VELO_ST_error_bank

    VELO_ST_pedestal_bank 

bulletBank data format for Muon

    Muon_bank_data_format

    Muon TELL1 input data format

bulletBank data format for OT

    OT_bank_data_format

 

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Specification of TELL1   

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Schematics TELL1.v4

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Layout and manufacturing Files on EDMS.v4 

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Board dimensions TELL1 board dimension

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Mechanical parts as front panel 

 

 

 

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