Home
Documentation
VHDL Framework
tell1lib c-code
Publications
Data Sheets
Known Bugs
Gallery
Links
Trigger Adapter
Optical Receiver
Analog Receiver
GBE
Front End Emulator
PVSS TELL1
Versions

VHDL Framework

VHDL Project resources for Mentor Graphics and Altera Quartus. During the development it is very difficult to work with CVS since the HLT Designer deletes directories containing the CVS information. Therefore the simplest way to export the VHDL framework design is to use a zip archive that can be downloaded from this website.

The FPGA firmware "pof file" you can download the c_code_only.zip file which includes the pof files and the corresponding c-code.

The CCPC c-code (tell1lib) consists of libraries to initialize and monitor all registers and memories of the board. It allows to run consistency checks by setting up the input data generator (on PP-FPGA) and comparing the result after processing. All parameters are set and kept in the configuration file.

The tell1lib and a few command line functions are available to be installed and updated via yum repository at Cern (see more information at tell1lib c-code).

Two CVS repositories are updated with each release. These are the c-code developed for the ccpc access and the vhdl text only exported files. The CVS repository can be accessed from the Cern CVS server at: TELL1 CVS

Version Date Comments Download/html
v4.2 17.6.2010 ****Release_v4.2*****
Common part

Detector Specific part
1.        LCMS and MCMS signal masking changed, new parameter and cfg version for Velo
hdl_release_v4.2.zip

 c_code_only.zip

 ecs_documentation

ecs_documentation_v4.2

v4.0.1 29.9.2009 ****Release_v4.0.1*****
Common part
Added some monitor counters in the SL for Error banks and throttles
Detector Specific part
1.        For the Velo added analog_link_disable bit
 
hdl_release_v4.0.1.zip

 c_code_only.zip

 ecs_documentation

ecs_documentation_v4.1

v3.2 12.2.2009 ****Release_v3.2*****
Common part
recompilation
Detector Specific part
1.        I2C for trigger adapter direct connection.
 
hdl_release_v3.2.zip

 c_code_only.zip

 ecs_documentation

v3.1 6.11.2008 ****Release_v3.1*****
Common part
1.  Correct the GBE port round robin FSM.
2.  ARP reply is always enabled even the GBE port is disabled for data flow
Detector Specific part
1.        EHCAl/PSSPD design updated by Nicolas.
 
hdl_release_v3.1.zip

 c_code_only.zip

 ecs_documentation

v3.0.2 9.10.2008 ****Release_v3.0.2*****
Update of the L0Muon and OT bug fix.
 
hdl_release_v3.0.2.zip

 c_code_only.zip

 ecs_documentation

v3.0 8.10.2008 ****Release_v3.0*****
Common part
1.  Added a function to check FE data for all sub-detectors. If no FE data accompanies TTC/ECS trigger, MEP generator will send out empty event.  This function is defiantly disabled Add FE_data_check_ctrl_register
2.  Added serious error throttle for all sub-detector.
3.  Added TTC parity check
4.  Added periodic NZS bank scheduler.
5.  Insert forced stop cycles for GBE flow control.
6.  GBE support auto-negotiation mode
7.  Add a tell1_selftest routine for hardware test
8.  L0fe_reset with one clock cycle delay!
9.  Added new data rate monitor registers for framer allowed data rate
10.          Added new parameters into the common part of cfg file.
11.          Some logic optimized for better timing
12.          byte calculation error fixed in SL_PP_Linker
New parameters added to the tell1 recipe, all default value can be used.
_L0013:___  0x[       0]  
_L0030:___  0x[       0]   
_L0031:___  0x[       0]  
_L0032:___  0x[       0]   
_L0033:___  0x[       0]   
_L0041:___     [       0]
Detector specific part
13.          Re-design the hdl and C codes for L0PUS.
14.          Added data generation and error check functionality for L0DU.
15.          Modified RX readout fsm and the setting of RX event size for L0DU
16.          header correction for ST
17.          arx links f disable or ST.
18.          error bank parser Corrected for OT.
19.          EHCAL and PSSPD specific HDL codes received from Nicolas on May 26. Fixed the fifo underflow bug for PSSPD by Nicolas on May 31.
20.          Added L0MUON specific HDL codes received from Jean-Pierre on May 20
21.          VELO Beetle pseudo header polarity correction
22.          fix ST/VELO algorithm bugs in both Firmware and Emulator (Pedestal/CMS/Cluster)
23.          NZS in case of error for VELO/ST (this cause TELL1 data structure change)
 
hdl_release_v3.0.zip

 c_code_only.zip

 ecs_documentation

v2.5 14.April 2008 ****Release_v2.5*****
1. Fix the bug in C code about the generation of ModelSim simulation init file (set_mem.do) for L0MUON.
2. Correct the wrong definition of bit width of SEP data fifo max usage (from 11 to 14) in C code.
Update the ECS document as well: SL_MAX_USE_REG ($0x001054).
3. Fix the bugs that orx link read/write event counts mismatch for L0CAL.
4. Replace two hdl files and fix the bugs that orx link read/write event counts mismatch for MUON.
5. Replace two hdl files for L0Du.
6. Change the scheme that pedestal banks are generated.
ECS document and CFG file generation code are modified as well.
7. Add two menus under C (tell1 control) in console_tell1:
(d) Disable all orx link
(c) Cancel the disable of all orx link
8. Replace detector_specific_vhdl_libraries for EHCAL and PSSPD.
Fixed a bug that ZS Link fifo and ZS data fifo will overflow after a few consecutive triggers.
9. Add a tell1 self test function which is called at the beginning of daq_tell1 and can be called by PVSS.
10. Fix a bug about the definition of ecs_reg_SL_ERROR_MON_REG_N.
11. Check MTU size setting in firmware. If ECS setting value is bigger than 8192, MTU size is assigned with 8192, otherwise, MTU size is equal to ECS setting value but 3 LSB are masked as 0. Notice: ECS setting value is equal to cfg file setting value minus 20.
12. Fix a bug that QDR CRC check state machine doesn’t work well when the length of MEP is too big.
13. Fix a bug that EVT_INFO_FIFO, DEST_IP_FIFO, TRIG_TYPE_FIFO and MEP_END_FIFO will overflow in the case that consecutive ECS triggers are sent too frequently.
14. Reduce the usage threshold of SL PP in fifo to make it safer.
 
hdl_release_v2.5.zip

 c_code_only.zip

 ecs_documentation

v2.4.4 20.March. 2008 1) QDR CRC check implemented " daq_tell1 -p shows the parity checking result"
2) Sync bus parity check implemented
3) Llink bus hardware  test implemented
4) Sync bus hardware test implemented
5) Random data generation with c-code "daq_tell1 -R"
6) ECS and QDR bus test available in the T command of the console_tell1
7) L0FE reset now used for resetting all but the configuration registers and RAM
8) Disable all optical links, only enabled for state running in PVSS
9) Fixed c-code bug when parsing large MEPs bigger than 64KByts
10) C-code added for PSSPD, error bank parser, parameter rebuild
 
hdl_release_v2.4.4.zip

 c_code_only.zip

 ecs_documentation

v2.4 5.March. 2008 1) c-code version field changed to expected firmware version field in SL
2) the L0Muon is the same transparent mode design
3) included the updated ehcal and psspd design from Nicolas
4) fixed the BER test for ehcal psspd (the clk 120 was not connected)
5) Fixed assymmetric CM subtraction for ST and VELO(Anne)
6) Fixed pedestal auto update bug in ST (Anne)
7) Fixed a shift in BCnt in the SL that was caused by a delay implemented for the testpulse generation, now the BCnt starts with 0x000 for the first bunch
8) Velo low_threshold now set to strip wise
9) Implement Parity check for QDR, LLINK and sync_info
10) Implement error_mon_reg in PPs and SL
11) Implement Velo headercorr. link wise
12) Implement ST headercorr. link wise
13) Implement Velo FIR
14) Implement MCMS for Velo
15) change processing order for Velo
 
hdl_release_v2.4.zip

 c_code_only.zip

 ecs_documentation

v2.3 30.11. 2007 1) fixed Velo hit threshold bug
2) reorder check now with threshold and reorder check combined
3) longer ttc reset pulse applied to solve ttc i2c access bug
4) fixed bug for concurrent banks in SL linker (caused erronous banks)
5) fixed to set the MEP factor in truncated MEPs to be zero length is 0x1C
6) Mirco found a bug for the error bank processing, error bank from only one pp makes the bank assembly to crash, always sent header word now
7) changed the sampling clock for ttcrx signals to be the falling edge, all signals are registered now !
8) added pptest and sltest reg that can be used to check access of the board without disturbing the processing
9) added monitor register for the last sent dest ip address by the ttc
10) fixed bug in the sl linker suggestion from mirco, changes from OT included!
 
hdl_release_v2.3.zip

 c_code_only.zip

 ecs_documentation

       
v2.1 and v2.1.1 (for c code) 6.Sept. 2007 1) L0CAL detector added.
2)Optimize the PP-Linker and SL-Linker FSM to achieve a better data throughput.
3) Added option to suppress the detector specific header in the ZS bank, also error checking on this data word is suppressed
3) The PP-Linker supports now a bank length interface for all bank types
4) Implement the EHCAL and PSSPD into the current framework to be used with the HDL-designer
5) ARP request are replyed now by the SyncLink-FPGA
6) Make new FIFO status monitoring system and implement it for all sub-detectors (not done for OT)
7) Check all sub-detector processing and its c-code representation
8) Fixed a bug in the priority of the ethernet and ip header ram access
9) Add a counter to check ip destination assignments from the ttc
10) Added documentation on the different sub-detector processing implementations
hdl_release_v2.1.zip c_code_only.zip ecs_documentation
v2.0 24.April 2007 1) Added the EHCAL VHDL and c-code support
2) Added the L0DU cfg support
3) Fixed a bug in the Velo DAC setting (dec->>hex)
3*) Fixed the dummy strip bug for Velo
4) Add the new IP dest scheme (Arthurs)
hdl_release_v2.0.zip c_code_only.zip ecs_documentation
v1.9.1 30.January 2007 1) Added the doxygen documentation to the c-code, use the vhdl from v1.9 c_code_only.zip
v1.6 25.July 2006 Internal release only  
v1.5

ST O-Rx
RICH O-Rx
(simple example)
VELO A-Rx
L0DU A-Rx

11.July 2006 1) Fixed a bug causing error for 1 word payload Ethernet frames (only occurred with overloaded Ethernet card)
2) Added a simple O-Rx design consisting of input buffering, unused link data suppression and data acquisition.
3) Made VHDL framework beeing installable at any location (relative path do work now)
4) Make Quartus work for synthesis now, ecs_reg bus usage has slightly changed.
hdl_release_1.5.zip c_code_only.zip html_access_Velo html_access_ST html_access_RICH ecs_documentation

 

 

 

Send mail to Guido.Haefeli@epfl.ch with questions or comments about this web site.